Source Level Debugging of Circuits Synthesized from High Level Language Descriptions

Karl Hemmert
The rapid increase in the density of modern FPGAs has allowed ever increasingly complex designs to be mapped to FPGAs. However, this increase in logic resources is accompanied by an increase in the complexity of describing and verifying the operation of an application. This has prompted the search for new approaches to the design, debug and verification of circuits. The desire to find more effecient approaches to designing these large FPGA circuits has led to...
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